The invention relates to multi-threaded bus master.
In computer systems having multiple layers of buses, bridge devices are used to allow bus devices to communicate among the different buses. For example, referring to FIG. 55, a computer system may contain a host bus 1001 connected to a central processing unit (CPU) 1000 and main memory 1002, a first Peripheral Component Interconnect (PCI) bus 1004, and a second PCI bus 1006. A CPU-PCI bridge 1008 allows communication from the host bus 1001 to the first PCI bus 1004, and a PCI-PCI bridge 1010 allows communication between the first and second PCI buses. Bus devices on a PCI bus capable of requesting bus ownership are referred to as bus masters. The bus masters on the first PCI bus 1004 include the PCI-PCI bridge 1010 and other peripheral bus devices 1012 and 1014.
Typically, the bus devices 1012 and 1014 are capable of having only one transaction outstanding at a time (and they are called single-threaded devices). For example, if the bus device 1012 generates a transaction on the first PCI bus 1004 targeted for the main memory 1002, but the CPU-PCI bridge 1008 determines that the main memory 1002 is busy (e.g., the CPU 1000 is accessing it), the CPU-PCI bridge 1008 would queue the transaction from the bus device 1012 and issue a retry (according to the PCI Local Bus Specification, Production Version, Revision 2.1 (June 1995)) to the bus device 1012 (retried bus device). After some amount of time, the retried bus device 1012 would attempt the same transaction. To prevent unnecessary grants to the retried bus master, the arbiter on the first PCI bus 1004 typically masks the requests (i.e., the request is ignored) from the retried bus master until the enqueued transaction has successfully been run on the target bus and a response is ready to be returned.
As the PCI-PCI bridge 1010 is connected to the second PCI bus 1006 which may be connected to more than one bus device, the PCI-PCI bridge 1010 is a bus master that can have more than one outstanding bus transaction simultaneously pending on the first PCI bus 1004 (the bridge 1010 is thus called a multi-threaded device). The PCI-PCI bridge 1010 forwards transactions from bus masters on the second PCI bus 1006 targeted at the first PCI bus 1004.